Low leakage SOI CMOS circuits based on the ultra-low power diode concept

The continuous scaling of CMOS technologies results in a strong increase of leakage currents in digital circuits. Reduction of static power dissipation is therefore an important issue, particularly in low-power system-on-a-chip (SoC) for mobile application where it has a large impact on the battery life. Static power dissipation in embedded memories is particularly crucial since those occupy a large area in VLSI circuits. Moreover, since the memories have to guarantee data storage, their power supply cannot be cut during long standby periods, unlike the other logic circuits. The present work aims at developing new circuits architectures to strongly reduce leakage currents in CMOS circuits, especially in storage elements. The proposed circuits rely on an original diode architecture made of two complementary MOSFETs, i.e. the Ultra-Low Power (ULP) diode. Negative gate-to-source voltage bias of the transistors in reverse mode results in ultra-low diode reverse current. This property makes the ULP diode particularly suited for the design of voltage multipliers (Dickson charge pumps) with high voltage multiplication factors, low power dissipation and high temperature functionality. As second interesting property, the ULP diode has a negative impedance characteristic in reverse mode. Based on this, a bistable element (ULP latch) is obtained by connecting two reverse biased ULP diodes in series. This bistable element can be used in any circuit requiring storage functionality, with a reduction of subthreshold leakage by orders of magnitude when compared with a conventional CMOS latch made of inverters. In this thesis, we model the ULP latch behavior for deep sub-micron technologies and investigate its properties. Our analysis relies on experimental characterization on various SOI CMOS technologies, up to 250°C. The feasibility of ultra-low leakage memory circuits based on the ULP latch is demonstrated experimentally by the design of SRAM circuits on a 0.13 µm Partially-Depleted SOI CMOS process. The great potential of the ULP latch to store the state of Multi-Threshold CMOS (MTCMOS) circuits during standby periods is demonstrated as well.