Performance Evaluation of An M/1-stage in An Atm Switching Element

The M/1-stage studied in this paper consists of M incoming lines who share a bus for the transmission of packets to an outgoing line. The capacity of the bus is DELTA-times higher than the speed of the incoming lines. The internal buffering is achieved by a common output buffer at the end of the bus. and by providing the crosspoints with small input buffers. The system is modeled as a finite capacity multi-queueing system with non-renewal input and cyclic non-exhaustive service discipline. The input processes belong to a class of tractable Markovian arrival processes (MAPs) introduced by Lucantoni, Meier-Hellstern and Neuts (1990), allowing the model to include bursty input traffic. Each buffer in the system is studied approximately by means of a finite capacity queue with repeated server vacations and limited service discipline, resulting in several performance measures of the system: the queue length distribution at an arbitrary time instant and at arrival instants for each queue, the loss probability of an arriving cell, the LST of the waiting time of an arriving cell. These results can be used to chose an optimal value for the factor DELTA, together with an accurate dimensioning of the buffers in the M/1-stage, in order lo minimize the chip size and such that the required performances (cell delay, delay jitter, cell loss) are guaranteed.