Power and area optimization of a dynamic vision sensor in 65nm CMOS

In this master thesis, a dynamic vision sensor (DVS) based on the DAVIS architecture is designed in 65nm CMOS. It aims at optimizing the architecture for this scaled technology. It firstly provides a overview of existing DVS architectures. An experimental analysis of different photodiodes is conducted to obtain both responsivity and dark current parameters. At the same time, a comparison between the four types of photodiode is done and results in the choice of an N-well/P-sub photodiode for this work. The pixel is then designed, based on the measured parameters, and following the target optimization in power and area. It ends up with an estimated 5µmx5µm pixel providing a power consumption of 16nW at high activity and 9nW of static power consumption. A latency of 7 µs and a dynamic range of 120dB are also reported but it is finally at the cost of increased contrast sensitivity (19 %) and FPN (9%). Problems encountered in this study are discussed and a set of design guidelines is proposed for future implementation of DVS in scaled CMOS technology.