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Hokkaido University Collection of Scholarly and Academic Papers >
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DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
| Title: | DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction |
| Authors: | YAMASHITA, Shigeru Browse this author | | MINATO, Shin-ichi Browse this author →KAKEN DB | | MILLER, D. Michael Browse this author |
| Keywords: | quantum circuit | | verification | | decision diagram |
| Issue Date: | Dec-2008 |
| Publisher: | 電子情報通信学会 |
| Journal Title: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume: | E91-A |
| Issue: | 12 |
| Start Page: | 3793 |
| End Page: | 3802 |
| Publisher DOI: | 10.1093/ietfec/e91-a.12.3793 |
| Abstract: | Recently much attention has been paid to quantum circuit design to prepare for the future “quantum computation era.” Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits. |
| Rights: | copyright©2008 IEICE |
| Type: | article |
| URI: | http://hdl.handle.net/2115/47392 |
| Appears in Collections: | 情報科学院・情報科学研究院 (Graduate School of Information Science and Technology / Faculty of Information Science and Technology) > 雑誌発表論文等 (Peer-reviewed Journal Articles, etc)
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Submitter: 湊 真一
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