Complexities of Layouts in Three-Dimensional VLSI Circuits
Aboelaze, Mokhtar A.; Wah, Benjamin W.
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https://hdl.handle.net/2142/74383
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Title Complexities of Layouts in Three-Dimensional VLSI Circuits Author(s) Aboelaze, Mokhtar A. Wah, Benjamin W. Issue Date 1987-02 Keyword(s) Cost Graph embedding One-active-layer layout Separator Three-dimensional layout Undirected graph Unrestricted layout VLSI complexity Volume Wire length Publisher Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG-87-2212, CSG-63 Type of Resource text Language English Permalink http://hdl.handle.net/2142/74383 Sponsor(s)/Grant Number(s) National Science Foundation / DMC 85-19649 Joint Services Electronics Program / N00014-84-C-0149 Egyptian Educational and Cultural Bureau scholarship
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