Bandgap engineering in vertical MOSFETs

Silicon CMOS devices have been scaled down continuously in the last few decades to improve the device performance, increase packing density and reduce cost. To further scale the transistor size below 100nm and achieve device performance improvement, new materials and new device structures have to be developed to meet all the challenges. The growth of high quality strained SiGe films has created new opportunities for the realization of new device structures using bandgap engineering in Si technology. Vertical MOSFETs have been employed in this study because there is more freedom in terms of bandgap engineering in a vertical format and the channel length is not dependent on the lithography. The key challenge in scaling of MOSFETs is to achieve adequate drive current and adequate turn-off simultaneously. Both SiGe channel vertical vii nMOSFETs and pMOSFETs show drive current improvement due to the enhancement of both hole and electron mobility in the vertical direction. However, the SiGe channel devices show larger drain-induced barrier lowering and increased leakage current. In another approach, a new device structure with SiGe in the source has been proposed and fabricated to suppress the short channel effects and reduce the leakage current. However, the drive current is also degraded due to the heterojunction between source and channel. The introduction of two-dimensional bandgap engineering, both in the gate-to-channel direction and source-to-channel direction, offers a further possibility to improve the device performance. Using this method, a novel pMOSFET with SiGe source and Si/SiGe/Si channel, which is called high mobility heterojunction MOSFET (HMHJT), has been realized and it shows both high drive current and low offstate leakage current. Finally, asymmetric channel devices have been investigated to improve short channel performance, reduce hot carrier effects and improve the drive current