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Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits
http://hdl.handle.net/2237/0002009458
http://hdl.handle.net/2237/00020094581331582b-ca35-491b-b7b7-f94613fb7afd
名前 / ファイル | ライセンス | アクション |
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e107-a_3_540.pdf (2.8 MB)
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Item type | itemtype_ver1(1) | |||||||||||
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公開日 | 2024-03-06 | |||||||||||
タイトル | ||||||||||||
タイトル | Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits | |||||||||||
言語 | en | |||||||||||
著者 |
LU, Jiaxuan
× LU, Jiaxuan
× MASUDA, Yutaka
× ISHIHARA, Tohru
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アクセス権 | ||||||||||||
アクセス権 | open access | |||||||||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||||||||
権利 | ||||||||||||
言語 | en | |||||||||||
権利情報 | Copyright(C)2024 IEICE | |||||||||||
内容記述 | ||||||||||||
内容記述 | Abstract Approximate computing (AC) saves energy and improves performance by introducing approximation into computation in error-torrent applications. This work focuses on an AC strategy that accurately performs important computations and approximates others. In order to make AC circuits practical, we need to determine which computation is how important carefully, and thus need to appropriately approximate the redundant computation for maintaining the required computational quality. In this paper, we focus on the importance of computations at the flip-flop (FF) level and propose a novel importance evaluation methodology. The key idea of the proposed methodology is a two-step fault injection algorithm to extract the near-optimal set of redundant FFs in the circuit. In the first step, the proposed methodology performs the FI simulation for each FF and extracts the candidates of redundant FFs. Then, in the second step, the proposed methodology extracts the set of redundant FFs in a binary search manner. Thanks to the two-step strategy, the proposed algorithm reduces the complexity of architecture exploration from an exponential order to a linear order without understanding the functionality and behavior of the target application program. Experimental results show that the proposed methodology identifies the candidates of redundant FFs depending on the given constraints. In a case study of an image processing accelerator, the truncation for identified redundant FFs reduces the circuit area by 29.6% and saves power dissipation by 44.8% under the ASIC implementation while satisfying the PSNR constraint. Similarly, the dynamic power dissipation is saved by 47.2% under the FPGA implementation. |
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言語 | en | |||||||||||
内容記述タイプ | Abstract | |||||||||||
出版者 | ||||||||||||
言語 | ja | |||||||||||
出版者 | 電子情報通信学会 | |||||||||||
言語 | ||||||||||||
言語 | eng | |||||||||||
資源タイプ | ||||||||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||||||||
タイプ | journal article | |||||||||||
出版タイプ | ||||||||||||
出版タイプ | VoR | |||||||||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||||
関連情報 | ||||||||||||
関連タイプ | isVersionOf | |||||||||||
識別子タイプ | DOI | |||||||||||
関連識別子 | https://doi.org/10.1587/transfun.2023VLP0008 | |||||||||||
収録物識別子 | ||||||||||||
収録物識別子タイプ | PISSN | |||||||||||
収録物識別子 | 0916-8508 | |||||||||||
書誌情報 |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 巻 E107A, 号 3, p. 540-548, 発行日 2024-03-01 |