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{"_buckets": {"deposit": "cadd4796-f763-44e9-b87e-257f3e2488f5"}, "_deposit": {"created_by": 3, "id": "7931", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "7931"}, "status": "published"}, "_oai": {"id": "oai:kanazawa-u.repo.nii.ac.jp:00007931", "sets": ["936"]}, "author_link": ["353", "377"], "item_4_biblio_info_8": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2010-01-01", "bibliographicIssueDateType": "Issued"}, "bibliographicPageStart": "5704666", "bibliographic_titles": [{"bibliographic_title": "ISPACS 2010 - 2010 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings"}]}]}, "item_4_description_21": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "This paper presents implementations of an FIR adaptive filter with a large number of taps on nVIDIA GeForce graphics processing unit (GPU) and CUOA software development environment. In order to overcome a long access latency for slow off-chip memory access, reduction of memory accesses by re-ordering and vector load/store operations and an increase of the number of threads are introduced. A tree adder is introduced to reduce the cost for summing thread outputs up. A simultaneous execution of multiple filters are also examined. On low-cost platform such as an Atom/ION nettop, GPU will accelerates the computation by almost three times. For simultaneous multiple simulations such as an ensemble averaging, a GPU with a large number of processing elements outperforms a dual-core CPU; almost six times faster for 16 runs. © 2010 IEEE", "subitem_description_type": "Abstract"}]}, "item_4_description_5": {"attribute_name": "提供者所属", "attribute_value_mlt": [{"subitem_description": "金沢大学理工研究域電子情報学系", "subitem_description_type": "Other"}]}, "item_4_publisher_17": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE = Institute of Electrical and Electronics Engineers"}]}, "item_4_relation_12": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isIdenticalTo", "subitem_relation_type_id": {"subitem_relation_type_id_text": "10.1109/ISPACS.2010.5704666", "subitem_relation_type_select": "DOI"}}]}, "item_4_version_type_25": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Hirano, Akihiro"}], "nameIdentifiers": [{"nameIdentifier": "377", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "70303261", "nameIdentifierScheme": "金沢大学研究者情報", "nameIdentifierURI": "http://ridb.kanazawa-u.ac.jp/public/detail.php?kaken=70303261"}, {"nameIdentifier": "70303261", "nameIdentifierScheme": "研究者番号", "nameIdentifierURI": "https://nrid.nii.ac.jp/nrid/1000070303261"}]}, {"creatorNames": [{"creatorName": "Nakayama, Kenji"}], "nameIdentifiers": [{"nameIdentifier": "353", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "00207945", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=00207945"}, {"nameIdentifier": "00207945", "nameIdentifierScheme": "研究者番号", "nameIdentifierURI": "https://nrid.nii.ac.jp/nrid/1000000207945"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-10-03"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "TE-PR-NAKAYAMA-K-5704666.pdf", "filesize": [{"value": "73.7 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 73700.0, "url": {"label": "TE-PR-NAKAYAMA-K-5704666.pdf", "url": "https://kanazawa-u.repo.nii.ac.jp/record/7931/files/TE-PR-NAKAYAMA-K-5704666.pdf"}, "version_id": "e01300b4-89f8-4f22-afce-068dcaecdd97"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Implementation of large-scale FIR adaptive filters on nVIDIA GeForce graphics processing unit", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Implementation of large-scale FIR adaptive filters on nVIDIA GeForce graphics processing unit"}]}, "item_type_id": "4", "owner": "3", "path": ["936"], "permalink_uri": "http://hdl.handle.net/2297/27097", "pubdate": {"attribute_name": "公開日", "attribute_value": "2017-10-03"}, "publish_date": "2017-10-03", "publish_status": "0", "recid": "7931", "relation": {}, "relation_version_is_last": true, "title": ["Implementation of large-scale FIR adaptive filters on nVIDIA GeForce graphics processing unit"], "weko_shared_id": -1}
Implementation of large-scale FIR adaptive filters on nVIDIA GeForce graphics processing unit
http://hdl.handle.net/2297/27097
http://hdl.handle.net/2297/27097ee440f59-0824-48e1-8258-8d6067b5dbcb
名前 / ファイル | ライセンス | アクション |
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TE-PR-NAKAYAMA-K-5704666.pdf (73.7 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | Implementation of large-scale FIR adaptive filters on nVIDIA GeForce graphics processing unit | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Hirano, Akihiro
× Hirano, Akihiro× Nakayama, Kenji |
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提供者所属 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 金沢大学理工研究域電子情報学系 | |||||
書誌情報 |
ISPACS 2010 - 2010 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings p. 5704666, 発行日 2010-01-01 |
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DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/ISPACS.2010.5704666 | |||||
出版者 | ||||||
出版者 | IEEE = Institute of Electrical and Electronics Engineers | |||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | This paper presents implementations of an FIR adaptive filter with a large number of taps on nVIDIA GeForce graphics processing unit (GPU) and CUOA software development environment. In order to overcome a long access latency for slow off-chip memory access, reduction of memory accesses by re-ordering and vector load/store operations and an increase of the number of threads are introduced. A tree adder is introduced to reduce the cost for summing thread outputs up. A simultaneous execution of multiple filters are also examined. On low-cost platform such as an Atom/ION nettop, GPU will accelerates the computation by almost three times. For simultaneous multiple simulations such as an ensemble averaging, a GPU with a large number of processing elements outperforms a dual-core CPU; almost six times faster for 16 runs. © 2010 IEEE | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |