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UBC Theses and Dissertations
Embedded test circuits and methodologies for mixed-signal ICs Tabatabaei-Zavareh, Sassan
Abstract
The rapid pace of the integrated circuit industry towards more miniaturization is making system-on-chip (SOC) a reality. For practical implementations of SOC, however, the test issues of such devices must be addressed through the integration of design-for-testability (DFT), built-in self-test (BIST), and embedded test for embedded blocks, such as digital, memory, and mixed-signal circuits. This thesis presents two novel embedded test solutions for mixed-signal circuits. The first one is a built-in current monitor (BICM) suitable for power supply current (IDD) testing. The B I CM includes a built-in current sensor (BICS) which provides high measurement sensitivity without introducing a large impedance in the IDD path. Although the BICS structure has been proposed before, the new circuit analysis and chip measurement results provide important insights into the BICS characteristics and design trade-offs. The BICM also includes a mixed-signal built-in current integrator (BICI) which generates a digital signature proportional to the average IDD (IDD)- TWO different circuits have been developed for BICI: a single-phase and a double-phase BICI; the first is less accurate but requires less silicon area. These new BICI architectures offer an advantage over previously proposed circuits because they can perform integration over large time windows (T > 1 ms) while occupying a chip area equivalent to a only few hundred NAND gates. The BICM is compact, accurate (error < 2%), and insensitive to process and temperature variations. The second embedded test circuit is designed for non-intrusive functional testing of high-speed clock-recovery units (CRU) and clock-synthesis units (CSU). To the author's knowledge, this new structure is the first circuit which can perform on-chip, single-shot jitter measurement with high resolution and precision without requiring element matching. The simulation and analysis predict a jitter measurement resolution of 10ps and a precision of 11ps in a 0.35 μm CMOS technology under typical power supply and thermal noise conditions. Combined with a jitter generator block, it can test intrinsic jitter, and jitter transfer characteristics of CRUs and CSUs. The circuit is digital, partially synthesizable, and automatically placeable and routable. Novel gate delay model and analysis techniques, supported by simulation, are also introduced to evaluate the accuracy of the circuit.
Item Metadata
Title |
Embedded test circuits and methodologies for mixed-signal ICs
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
2000
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Description |
The rapid pace of the integrated circuit industry towards more miniaturization is making
system-on-chip (SOC) a reality. For practical implementations of SOC, however, the test
issues of such devices must be addressed through the integration of design-for-testability
(DFT), built-in self-test (BIST), and embedded test for embedded blocks, such as digital,
memory, and mixed-signal circuits.
This thesis presents two novel embedded test solutions for mixed-signal circuits. The
first one is a built-in current monitor (BICM) suitable for power supply current (IDD) testing.
The B I CM includes a built-in current sensor (BICS) which provides high measurement
sensitivity without introducing a large impedance in the IDD path. Although the BICS
structure has been proposed before, the new circuit analysis and chip measurement results
provide important insights into the BICS characteristics and design trade-offs. The BICM
also includes a mixed-signal built-in current integrator (BICI) which generates a digital signature
proportional to the average IDD (IDD)- TWO different circuits have been developed
for BICI: a single-phase and a double-phase BICI; the first is less accurate but requires less
silicon area. These new BICI architectures offer an advantage over previously proposed
circuits because they can perform integration over large time windows (T > 1 ms) while
occupying a chip area equivalent to a only few hundred NAND gates. The BICM is compact, accurate (error < 2%), and insensitive to process and temperature variations.
The second embedded test circuit is designed for non-intrusive functional testing of
high-speed clock-recovery units (CRU) and clock-synthesis units (CSU). To the author's
knowledge, this new structure is the first circuit which can perform on-chip, single-shot jitter
measurement with high resolution and precision without requiring element matching.
The simulation and analysis predict a jitter measurement resolution of 10ps and a precision
of 11ps in a 0.35 μm CMOS technology under typical power supply and thermal noise conditions.
Combined with a jitter generator block, it can test intrinsic jitter, and jitter transfer
characteristics of CRUs and CSUs. The circuit is digital, partially synthesizable, and automatically
placeable and routable. Novel gate delay model and analysis techniques, supported
by simulation, are also introduced to evaluate the accuracy of the circuit.
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Extent |
7296425 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-07-23
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065266
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2000-11
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.