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Study of near-surface stresses in silicon around through silicon vias at elevated temperatures by Raman spectroscopy and simulations

University of British Columbia

Three-dimensional (3-D) integration has emerged as an effective solution to overcome the wiring limit imposed on device density and performance with continued scaling. Through silicon vias (TSVs), which provides interconnection between stacked chips, are essential for the 3-D integration. However, due to the large mismatch of the thermal expansion coefficients (CTEs) between via-filling material (Cu) and Si, thermal stresses induced during processing can result in undesirable mobility shifts in devices and serious reliability problems. In this work, the near-surface stress distributions around TSV structures were studied using both experimental and numerical approaches. Stress measurements and characterizations by micro-Raman spectroscopy at elevated temperatures are conducted to study the stress origin and evolution in TSV structures. Micro-Raman spectroscopy measures a combination of tensile and compressive near-surface stresses in the Si around TSVs. The results show that increasing the sample temperature towards the annealing temperature of the TSV sample will reduce the near-surface stresses around the TSVs. Temperature dependent measurements reveal that the stresses near TSVs have two components: 1) pre-existing stress before via filling, and 2) CTE mismatch-induced stress. To further understand the origins of the stress fields near TSVs, various TSV structures and via-filling materials are studied. The CTE mismatch-induced stress can be simulated by finite element analysis. The results obtained from the micro-Raman measurements are compared with the simulations. In particular, the differential values between the experimental data and simulation results are extracted in order to estimate the pre-existing stresses in the TSV structures. Once the pre- iii existing stress component is taken into account, a good agreement between the Raman measurement and the finite element calculation is obtained. The CTE-mismatch-induced stress resulted mobility change and keep-out zone (KOZ) at elevated temperatures are also estimated. Higher temperatures are shown to reduce the CTE-mismatch-induced stress component, and result in the shrinkage of KOZs in Si. The pre-existing stress is shown to be significant in a region equal or larger than the KOZs induced by CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and circuit design.

Text

2014-12-18

Attribution-NonCommercial-NoDerivs 2.5 Canada

http://hdl.handle.net/2429/51590

Materials Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/2.5/ca/