Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique

The operational amplifier (op-amp) is one of the most commonly used analogue circuits for analogue and mixed-signal Integrated Circuit (IC) designs. The op-amp is widely designed using a sub-micron Complementary Metal-Oxide-Semiconductor (CMOS) technology, for example, by making use of 0.35, 0.18, and 0.13 μm technology nodes. However, there are different techniques available to design the op-amp for different circuit requirements. For example, rail-to-rail operation is a common requirement for low-voltage operation where rail-to-rail operation can denote the input, the output, or both input and output, and, have a dynamic range that can reach the limits, or close to the limits, of the power supply voltage. However, all op-amps are required to have a suitable open-loop margin of stability in order for them to be used in a negative feedback closed-loop configuration with an appropriate frequency response. Therefore, open-loop configuration should have a 45° or higher phase margin, which is achieved by using compensation techniques. Different compensation techniques could, therefore, be employed to achieve a required stability and frequency response. These compensation schemes could be employed individually or in combinations. In this work, techniques for op-amp compensation are identified and evaluated. The compensation schemes considered in this work are conventional (direct), indirect, and negative Miller compensation. A requisite condition for the op-amp designs is that they need to work at low-voltage and low-power. For low-voltage operation, the op-amp is designed using the gm/ID approach for the purpose of determining transistor dimensions. Each op-amp design is based on a single-rail power supply operating at, or below, +3.3 V. Moreover, the op-amp is designed such that the transistors can operate in weak and moderate inversion regions in addition to strong inversion. A serious drawback of transistor circuit designs operating in weak and moderate inversion is that it can reduce the frequency response performance of the op-amp. Direct and indirect Miller capacitances are used to reach the required margin of stability. However, by applying the negative Miller capacitance (negative Miller compensation) to specific nodes within the circuit, the amplifier bandwidth can be increased. The compensation techniques are considered within a two-stage CMOS op-amp with both single-ended and fully differential outputs. Negative Miller capacitance is used around the first stage whilst direct and indirect Miller capacitances are used around the second stage. The outline of this thesis is as follows. Chapter 1 will introduce the work undertaken in this research project, considering low-voltage and frequency response issues. The novel aspects of the work completed will also be identified. Chapter 2 will provide an overview of the MOSFET transistor large and small-signal operation as well as describing the gm/ID design approach. The gm/ID design approach is considered as it is suitable for use in low-voltage, low power analogue circuit design. Chapter 3 will introduce the two-stage CMOS op-amp architecture and amplifier compensation techniques used in work. Specifically, conventional (direct), indirect and negative Miller compensation have been utilised. Chapter 4 will present the rail-to-rail single ended output op-amp with Cadence Spectre simulation study results and a physical prototype device that was fabricated using the Austria Mikro Systeme (AMS) 0.35 μm n-well CMOS fabrication process. Chapter 5 will present the rail-to-rail CMOS op-amp with a fully-differential output. Chapter 6 will focus on the design and operation of a programmable op-amp and will present two different programming approaches. Chapter 7 will provide conclusions to the work and identify future research directions.