Characteristics of the higher-k Hf-Zr-O dielectric materials on Si & Ge substrates and their application in 3-dimensional Tri-Gate FET devices

Abstract

The tremendous success of complementary metal oxide semiconductor (CMOS) technology over the past four decades and, as a result, the significant progress of information technology in general are based, to a large extent, on a simple gift of nature, the SiO2/Si system. This is especially true because ultrathin gate dielectrics in metal oxide semiconductor field effect transistors (MOSFETs) remain the key element in conventional silicon-based microelectronic devices. Since the very beginning of the microelectronics era, the SiO2 gate oxide has played a critical role in device performance and scaling. A potential barrier controlled by the gate field modulates the current flow from source to drain. Its simplicity, together with the fact that it is available in complementary n-FET and p-FET versions, is underlying basis for the success of CMOS technology. However, fundamental physical limits have heralded the end of conventional linear scaling of transistor dimensions, and a new era of MOSFET scaling constrained by power dissipation and process-induced variations is already here. Beyond the fundamental scaling method, high-k gate oxide materials, which were replacing SiO2, were strongly required. Scaling of the gate stack has been a key to enhance CMOS field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. From this stems, recently, Hf-based high-k metal gate (HKMG) process was introduced into the industrial technology from 45nm device generaton node. However, this remarkable application is still in challenge as technogy node goes down more, further engineering works for achieving the higher-k dielectric materials is strongly pursued. Moreover, beyond the 22 nm node, where gate lengths have almost less than 10 nm, it is still controversial whether planar CMOS devices would be a practical option because of dopant fluctuations, control of SCEs, and other problems. Multigate MOSFETs such as FinFETs or Tri-Gate FET may provide better electrostatic control, Recenly, this 3D dimensional device is starting to come out in the business field, however, these devices still have their own limitations in terms of actual device fabrication difficulties and cost increase. Other engineering works that could give a relaxation room for scaling limitation are to implementing alnernative channel materials which has a high carrier mobility such as Ge, GaAs. Especially, Gemanium is a promsing candidate to replace Si in the future beyond scaling devices due to its narrow band gap, high mobility, and low dopant activation temeperatures. But, unlike with Si, it is difficult to grow an insulating oxide on Ge comparable to SiO2/Si, thus, the lack of thermodynamic stability at the high-k/Ge interface hampers the development of Ge metal-oxide-semiconductor (MOS) devices due to the desorption of GeO. Therefore, researches on surface treatment of Ge substrate or passivation layer implementation between Ge substrate and the high-k oxide are strongly required. In this works, from the stems of above engineering ingenuity, following 3 topics are investigated: (1) Phase control of HfO2-based dielectric films for the higher -K materials, (2) Passivation layer effects on the oxy-nitridation treated Ge substrate, (3) Fabrication of a nano-scaled tri-gate FET using step-down patterning and dummy gate processes. In the first part, attempts were made to increase the k values of the HfO2 film by transforming its structure from monoclinic to tetragonal phase. The tetragonal seed HfO2 layer and multilayer approaches were tested based on the fact that the HfO2 film deposited via atomic layer deposition (ALD) using O2 as the oxygen source induced tetragonal-phase HfO2 after the post-deposition annealing (PDA) at temperatures higher than 700oC. Both approaches, however, failed to transform the monoclinic HfO2 layer grown via ALD using O3 as the oxygen source, which suggests that the driving force for forming the thermodynamic stable phase (monoclinic) overwhelms the interface energy effect between the two different phases, which would have induced the desired transformation. As another approach, the HfO2 films were alloyed with ZrO2 (HZO film), which was an effective method of changing the structure from monoclinic to tetragonal. While the k values of the HZO film could be tuned by the Zr concentration and the PDA temperature, the increase of the PDA temperature to over 800oC induced the compositional segregation of HZO, which largely increased the leakage current. A critical Zr concentration was found (between 50 and 70%), in which the k-value increase was quite abrupt but the increase in leakage was not very evident after the PDA at 700oC. Secondly, oxy-nitridation (GeOxNy) surface treatment by NH3 + O2 gas ambiment RTA (rapid thermal annealing) process on Ge substrate were investigated. 550℃, 1min annealing induced 0.5nm ultra-thin GeOxNy layer, and it gave remarkably reduced Vhy about 25~30% and Dit value of 9.8x 1011cm-2eV-1 on the Ge / GeOxNy / Hf-Zr-O / TiN, High-k metal gate stacks. In addition to GeOxNy implementation, passivation layer (PL) effects using SiO2, SiAlxOy and Al2O3 were studied with the various PDA temperatures from as-deposited (room temperature) to 650 oC. SiO2 PL groups shows most minimized Vhy (≒140mV), Dit (≒8.5x1011) in the without PDA condition, however, as PDA temperature went up to 650 oC, Vhy and Dit values of SiO2 PLs group were getting worse than Al2O3 PL group. From the XPS analysis and HR-TEM images, in SiO2 PL group, GeO redox is more intensively observed and thermally re-growth passivation layer was detected with the out-diffused Ge elements in the PL layer region. That means SiO2 oxide is more unstable in the passivation layer application, compared to Al2O3. This is also reason why oxygen bonding enthalpy of SiO2(≒368 kJ/mol) is smaller than that of Al2O3 (≒512 kJ/mol). Therefore, Al2O3 has a high candidate for passivation layer application for maintaing device immunity by heat budget. Thirdly, the process sequence and device performances of the three-dimensional tri-gate field effect transistor (TGFET) were reported, where a fin-shaped Si channel with a 20 nm channel width and an 80 nm fin height was fabricated using the conventional i-line stepper, assisted by the double hard mask step-down (DHMSD) lithography process. The channel length was 150 nm. An atomic-layer-deposited Al2O3 and Hf0.51Zr0.49O2 film with an equivalent oxide thickness of 1.9, 0.9nm respectively, and a TiN layer grown through another atomic layer deposition process were adopted as the high-k and metal gate, using the dummy gate process. The device performance was compared with that of the planar FET simultaneously fabricated on the same Si wafer. The ion implantation and Ni-silicide processes were also optimized for this process sequence. Both n- and p-type devices were fabricated. The TGFET showed a high on/off current ratio of ~106, a low subthreshold swing of 77mV/dec for the n-type device, and a small drain-induced barrier lowering of 35 mV for the n-type device, which were remarkably improved device performances compared with the planar FET device. These improvements were due to the improvement of the electrostatic control of the fin-shaped channel by the tri-gates, which coincides with the theoretical expectation and previous experiment results. Nevertheless, the p-type devices showed inferior performances compared with the n-type devices due to the excessive dopant diffusion from the source and drain regions into the channel. As above, from the higher-k gate oxide engineering on Si and Ge substrate to investigations on its applicable 3D structure tri-gate FET fabrication, comprehensive activities were excuted with various analysis tools and knowledges.