Accelerating host-compiled simulation by modifying IR code: industrial application in the spatial domain
Ver/ Abrir
Registro completo
Mostrar el registro completo DCFecha
2019Derechos
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publicado en
34th Conference on Design of Circuits and Integrated Systems (DCIS), Bilbao, 2019
Editorial
Institute of Electrical and Electronics Engineers Inc.
Enlace a la publicación
Resumen/Abstract
Space applications rely on long and complex design processes, as they must deal with strict non-functional requirements such as criticality, timeliness, reliability and safety. The huge number of analysis and evaluations performed requires powerful simulations technologies combining high simulation speed and accuracy. Host-compiled simulation is a powerful approach to achieve fast, timed simulation of software running in complex embedded systems. However, in the general term, there is still the need of improving the speed and accuracy of these solutions, and there is a lack of host-compiled approaches oriented to space applications. To solve the first point, this paper presents an alternative that modifies the standard solution of adding the modeling of the cross-compiled control flow in the host computer by modifying the compiler's intermediate representation. That way, the host binary naturally follows the cross-compiled binary flow, avoiding a separate modeling, and improving simulation speed while maintaining accuracy. Additionally, the paper focuses on LEON processor, commonly used by the European Space Agency (ESA).
Colecciones a las que pertenece
- D50 Congresos [449]
- D50 Proyectos de Investigación [361]