Analogcircuit/IC design for high speed optical fiber communication is a fairly new research area in Dr. Ha's group. In the first project sponsored by ETRI (Electronics and Telecommunication Research Institute) we started to design the building blocks of receiver for next generation 400 Gb/s optical fiber communication. In this thesis research a transceiver architecture based on 4x100 Gb/s parallel communication is proposed. As part of the receiver, a transimpedance amplifier for 100 Gb/s optical communication is designed, analyzed and simulated. Simulation results demonstrate the excellent feasibility of proposed architecture.

Bipolar technology based on III-V materials (e.g. - GaAs, InP based HBT, HEMT) has always dominated the high speed optical transceiver design because of their inherent properties of high mobility and low noise. But they are power hungry and bulky in size which made them less attractive for highly integrated circuit design. On the contrary, CMOS technology always drew attraction because of low cost, low power dissipation and high level of integration facility. But their notorious parasitic characteristic and inferior noise performance makes high speed transceiver design very challenging. The emergence of nano-scale CMOS offer highly scaled feature sized transistors with transition frequencies exceeding 200 GHz and can improve optical receiver performance significantly.

Increasing bandwidth to meet the target data rate is the most challenging task of TIA design especially in CMOS technology. Several CMOS TIA architectures have been published recently [6]-[11] for 40 Gb/s data rate having bandwidth no more than 40 GHz. In contrast to existing works, the goal of this research is to step further and design a single channel stand-alone TIA compatible in serial 100 Gb/s data rate with enhanced bandwidth and optimized transimpedance gain, input referred noise and group delay variation.

A 100 Gb/s transimpedance amplifier (TIA) for optical receiver front end is designed in this work. To achieve wide bandwidth and low group delay variation a differential TIA with active feedback network is proposed. Proposed design also combines regulated cascode front end, peaking inductors and capacitive degeneration to have wide band response. Simulation results show 70 GHz bandwidth, 42 dBΩ transimpedance gain and 2.8 ps of group delay variation for proposed architecture. Input referred noise current density is 26 pA/â while the total power dissipation from 1.2V supply is 24mW. Performance of the proposed TIA is compared with other existing TIAs, and the proposed TIA shows significant improvement in bandwidth and group delay variation compared to other existing TIA architectures.