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A probabilistic and timed verification approach of SysML state machine diagram
Baouya, Abdelhakim; Bennouar, Djamal; Mohamed, Otmane Ait et al.
2015In A probabilistic and timed verification approach of SysML state machine diagram
Peer reviewed
 

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Disciplines :
Computer science
Author, co-author :
Baouya, Abdelhakim
Bennouar, Djamal
Mohamed, Otmane Ait
Ouchani, Samir ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT)
External co-authors :
yes
Language :
English
Title :
A probabilistic and timed verification approach of SysML state machine diagram
Publication date :
2015
Event name :
12th International Symposium on Programming and Systems (ISPS), 2015
Event organizer :
IEEE
Event date :
2015
Main work title :
A probabilistic and timed verification approach of SysML state machine diagram
Peer reviewed :
Peer reviewed
Commentary :
1--9
Available on ORBilu :
since 23 February 2016

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