Soft decoding of convolutional product codes on an FPGA platform

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2005

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Sanlı, Mustafa

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In today̕s world, high speed and accurate data transmission and storage is necessary in many fields of technology. The noise in the transmission channels and read-write errors occurring in the data storage devices cause data loss or slower data transmission. To solve these problems, the error rate of the received information must be minimized. Error correcting codes are used for detecting and correcting the errors. Turbo coding is an efficient error correction method which is commonly used in various communication systems. In turbo coding, some redundancy is added to the data to be transmitted. The redundant data is used to recover original data from the received data. MAP algorithm is one of the most commonly used soft decision decoding algorithms. In this thesis, hardware implementation of the MAP algorithm is studied. MAP decoding is verified on an FPGA. Virtex2Pro is the platform of choice in this study. The algorithm is written in the VHDL language. A MAP decoder is designed and its operation is verified. Using many MAP decoders concurrently, a convolutional product decoder is implemented as well. Area and speed limitations are discussed.

Subject Keywords

Computer engineering.

URI

http://etd.lib.metu.edu.tr/upload/2/12606572/index.pdf
https://hdl.handle.net/11511/15446

Collections

Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

M. Sanlı, “Soft decoding of convolutional product codes on an FPGA platform,” M.S. - Master of Science, Middle East Technical University, 2005.