Title:
Study of III-N heterostructure field effect transistors
Study of III-N heterostructure field effect transistors
Author(s)
Narayan, Bravishma
Advisor(s)
Shen, Shyh-Chiang
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Abstract
This thesis describes the design, fabrication and characterization of AlGaN/GaN Heterostructure Field E ect Transistors (HFETs) grown by a Metal Organic Chemical Vapor Deposition (MOCVD) on sapphire substrates. The objective of this research is to develop AlGaN/GaN power devices with high breakdown voltage (greater than 1 kV) and low turn-on resistance. Various characteristics such as current drive (Idss), transconductance (gm) and threshold voltage (Vth) have also been measured and the results have been discussed. Two major challenges with the development of high breakdown voltage AlGaN/GaN HFETs in the past have been high material defect density and non-optimized fabrication technologies which gives rise to bu er leakage and surface leakage, respectively. In this thesis, mesa isolation, ohmic and gate metal contacts, and passivation techniques, have been discussed to improve the performance of these power transistors in terms of low contact resistance and low gate leakage. The relationship between breakdown voltage and Rds(ON)A with respect to the gate-drain length (Lgd) is also discussed. First, unit cell devices were designed (two-fingered cells with Wg = 100, 300, 400 m) and characterized, and then they were extended to form large area devices (upto Wg = 40 mm). The design goals were classied into three parts:
- High Breakdown Voltage: This was achieved by designing devices with variations in Lgd,
- Low turn-on resistance: This was achieved by optimizing the annealing temperatures as well as incorporating additional thick metal pads, as well as optimizing the passivation etch recipe,
- Low Gate Leakage: The gate leakage was reduced signicantly by using a gate metal with a larger barrier height.
All devices with Lgd larger than 10 m exhibited excellent breakdown voltage characteristics of over 800 V, and it progressed as the Lgd increased. The turn-on resistance was also reduced signicantly below 20 m-cm2, for devices with Lgd = 15, 25, and 20 m. The gate leakage was measured for all devices upto 200 V, and was in the range of 10-100 nA, which is one of the best values reported for multi-ngered devices with Lgd in the range of 2.4-5 mm. Some of the key challenges faced in fabrication were determining a better gate metal layer to reduce gate leakage, optimizing the passivation via etch recipe, and reducing surface leakage.
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Date Issued
2010-09-01
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