Title:
Analysis and optimization of global interconnects for many-core architectures
Analysis and optimization of global interconnects for many-core architectures
Author(s)
Balakrishnan, Anant
Advisor(s)
Naeemi, Azad
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Abstract
The objective of this thesis is to develop circuit-aware interconnect technology
optimization for network-on-chip based many-core architectures. The dimensions of
global interconnects in many-core chips are optimized for maximum bandwidth density
and minimum delay taking into account network-on-chip router latency and size effects
of copper. The optimal dimensions thus obtained are used to characterize different
network-on-chip topologies based on wiring area utilization, maximum core-to-core
channel width, aggregate chip bandwidth and worse case latency. Finally, the advantages
of many-core many-tier chips are evaluated for different network-on-chip topologies.
Area occupied by a router within a core is shown to be the bottleneck to achieve higher
performance in network-on-chip based architectures.
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Date Issued
2010-12-02
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Text
Resource Subtype
Thesis