This thesis presents the results of a study of the effect of various interconnection network parameters on the performance of applications running on a scalable shared-memory multiprocessor. We developed a modular simulator for shared-memory multiprocessors called MEMSIM. This simulator, which was developed as a part of the Rice Parallel Processing Testbed, was used in all the experiments described in this thesis. The architecture simulated was a shared-memory multiprocessor with 64 processing nodes, with full bit-map directory-based coherence protocol. The performance of four network topologies: mesh, hypercube, and two shuffle-exchange networks were compared in our experiments. Four applications were used in our experiments: Fast Fourier Transform, Bimerge, Matrix Multiply and Successive Over Relaxation. The main results of our study can be summarized as follows: (1) With constant bisection width, the mesh network outperforms all the other network topologies; (2) Cache miss rate largely influences the relative performance of different network configurations.