High performance hardware implementation of elliptic curve cryptography

Elliptic curve cryptography (ECC), a public-key cryptography (PKC) encryption technique, has gained much interest among cryptography researchers because of its advantages over other commonly used PKC algorithms, such as the Rivest,Shamir and Adleman (RSA) cryptosystem. It offers equivalent security to RSA,but with significantly shorter key lengths. This attractive feature makes ECC very popular for resource-constrained applications such as smart cards, creditcards, pagers, personal digital assistants (PDAs), and cellular phones. ECC is considered to be more efficient in terms of speed, area, and power consumption. This dissertation introduces several hardware implementations of an efficient ECC cryptosystem both on a field-programmable gate array (FPGA) and on an application-specific integrated circuit (ASIC) using VHDL. The first half of this dissertation discusses the high-performance hardware implementation of an ECC over the binary field F2m and the second half describes an efficient implementation of an ECC over the prime field Fp. These are implemented both in affine and Jacobian coordinates using the binary method (i.e. the double-and-add method) and the National Institute of Standards and Technology (NIST) recommended standard. The performance or efficiency of an ECC processor (ECP) is based on elliptic curve scalar (or point) multiplication (ECSM or ECPM) which is the most time and resource consuming operation in either a binary field or a prime field.The aim of this dissertation is to implement an efficient ECPM with a tradeoff between speed, energy, and area complexities, required for modern security applications. Various techniques are introduced to improve the performance of the ECPM, such as parallelisation, pre-computations, algorithm or architectural optimisation, and improved finite-field (or modular) arithmetic architectures. Although there is a substantial amount of work on separate point doubling (PD) and point addition (PA) implementations to compute elliptic curve group operations, essential for an ECPM, not much work is focused on a combined hardware architecture for group operations. In this research work, both modular arithmetic and group operations are optimised to improve the performance of ECPM. A combined PDPA architecture is designed which performs the PD and PA operations together in each iteration. Consequently, a uniform power consumption profile may be measured throughout the PDPA hardware, hence the point multiplication computation. Therefore, the proposed ECPM hardware implementation is secure against timing attacks and simple power analysis (SPA) attacks. In this dissertation, the parallel ECPM architecture supports two Koblitz and random curves for the key sizes 163 and 233 bits and the ECP using a bit-serial multiplier supports all five NIST curves for the key sizes from 163 to 571 bits. The delay of a 233-bit parallel point multiplication is only 3.05 μs in a Xilinx Virtex-7FPGA and 0.81 μs in an ASIC 65-nm technology. In addition, an energy-efficient ECP implementation over F2m is achieved in which the Area x Time x Energy value is lower in an ASIC platform than in all comparable work in the literature. On the other hand, an ASIC-based implementation of an ECP over prime fields supports three prime fields of the five NIST-recommended primes p, with sizes 192, 224, and 256 bits. The delay for ASIC-based ECP over Fp is between 0.207 and 0.366 ms. To the best of the author’s knowledge, these are the fastest hardware implementation result reported in the literature to date. Moreover, the energy dissipation is only about 0.3% of that of other similar designs.