Design verification of power electronics systems subject to bounded uncertain inputs

Hope, Eric M.

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https://hdl.handle.net/2142/14643 Copy

Description

Title

Design verification of power electronics systems subject to bounded uncertain inputs

Author(s)

Hope, Eric M.

Issue Date

2010-01-06T16:20:20Z

Director of Research (if dissertation) or Advisor (if thesis)

Domínguez-García, Alejandro D.

Doctoral Committee Chair(s)

Domínguez-García, Alejandro D.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• power electronics
• design verification
• power converters
• reachability analysis
• switched-linear systems

Abstract

This thesis proposes a new methodology for design verification of power electronics systems subject to bounded uncertain inputs. In this method, the power electronics system, which consists of the power electronics converter circuit and the associated controller, is described by a switched-linear state-space representation, where some or all of the inputs may vary without control over some bounded range (e.g. load current, source voltage). The method relies on the solution to the reachability problem associated with this system, which is the computation of the set of all possible system trajectories that arise from different initial conditions, uncontrolled inputs, and inherent switching. The system design verification problem is solved by verifying that this set, called the reach set, remains within a region of the state-space defined by performance requirements (e.g. output voltage tolerance specifications, component voltage and current limits). Algorithms to solve the reachability problem for power electronics converters operating under both open-loop and closed-loop control are provided. The application of this method is illustrated through buck and boost converter simulation examples. Experimental validation of the method is carried out in a buck converter. Existing power electronics system design verification methods rely heavily on time-domain simulations. For each simulation, the set of possible inputs is randomly sampled to obtain a particular operating condition. A very large number of simulations are required in order to verify the behavior of the system for all possible operating conditions. These simulation-based methods also typically rely on the small-signal average model of the power electronics system. This model ignores the effects of switching and is only valid for small perturbations around the nominal operating point of the system. With the proposed methodology, it is only necessary to solve one set of matrix differential equations to account for all possible operating conditions. Furthermore, the proposed method uses a switched-linear model of power electronics systems, which is capable of capturing the full large-signal behavior of the system. Thus, the proposed methodology aims to produce a complete and computationally tractable solution to the power electronics system design verification problem.

Graduation Semester

2009-12

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http://hdl.handle.net/2142/14643

Copyright and License Information

Copyright 2009 Eric M. Hope

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