The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption
Faust, Adam
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https://hdl.handle.net/2142/26032
Description
Title
The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption
Author(s)
Faust, Adam
Issue Date
2011-08-25T22:09:57Z
Director of Research (if dissertation) or Advisor (if thesis)
Rosenbaum, Elyse
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Electrostatic Discharge (ESD)
Serial I/O
Signal Integrity
Equalization
Abstract
For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level and implementation options of the ESD protection circuit designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into power estimates to demonstrate the power versus reliability trade-off. Essentially, rather than approaching the effect of ESD protection circuits as harmful, this work approaches the effect of ESD protection circuits as an engineering optimization problem which requires co-design between the printed circuit board (PCB) designer, transmitter and receiver circuit designer, and ESD protection circuit designer.
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