Design automation for circuit reliability and energy efficiency

Lin, Chen-Hsuan

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https://hdl.handle.net/2142/99237 Copy

Description

Title

Design automation for circuit reliability and energy efficiency

Author(s)

Lin, Chen-Hsuan

Issue Date

2017-12-05

Director of Research (if dissertation) or Advisor (if thesis)

Chen, Deming

Doctoral Committee Chair(s)

Chen, Deming

Committee Member(s)

• Hwu, Wen-Mei
• Rutenbar, Rob A.
• Wong, Martin D. F.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Electronic design automation
• Reliability
• Energy efficiency
• Data mining
• Satisfiability (SAT) solving
• Logic restructuring
• Assertion
• Negative bias temperature instability (NBTI) effect
• Modulo arithmetic
• Shadow datapath

Abstract

This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety of algorithmic methods and heuristics are used in our approaches such as SAT solving, data mining, logic restructuring, and applied mathematics. Furthermore, the scalability of our approaches was taken into account while we developed our solutions. Experimental results show that our approaches offer the following advantages: 1) SAT-BAG can generate concise assertions that can always achieve 100% input space coverage. 2) C-Mine-DCT, compared to a recent publication, can achieve compatible performance with an additional 8% energy saving and 54x speedup for bigger benchmarks on average. 3) C-Mine-APR can achieve up to 13% more energy saving than C-Mine-DCT while confronting designs with more common cases. 4) CSL can achieve 6.5% NBTI delay reduction with merely 2.5% area overhead on average. 5) Our modulo functional units, compared to a previous approach, can achieve a 12.5% reduction in area and a 47.1% reduction in delay for a 32-bit mod-3 reducer. For modulo-15 and above, all of our modulo functional units have better area and delay than their previous counterparts.

Graduation Semester

2017-12

Type of Resource

text

Permalink

http://hdl.handle.net/2142/99237

Copyright and License Information

Copyright 2017 Chen-Hsuan Lin

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