Error correction codes in NAND flash memory

Error Correction Codes (ECC) are used in NAND Flash memories to detect and correct bit-errors. With shrinking technology nodes and increased memory complexity, bit error rates continue to grow. With mainstream usage of MLC/TLC devices where 2 or 3 bits of data are stored in each Floating-Gate transistor, this issue has become even more critical, and to address this, strong ECC schemes are being implemented. ECC is a good way to recover the wrong value from the remaining good bits, and robust error correction codes ensure data integrity. This work discusses the operation of Floating-Gate transistors and NAND Flash memory. Various causes of bit-errors in these memories such as Read Disturb, repeated Program/Erase cycles and Program Disturb are presented. Analysis of various ECC schemes such as Hamming Codes, Bose, Chaudhuri, and Hocquenghem (BCH) codes and Reed-Solomon codes and their implementation in NAND Flash memory is examined. The encoding-decoding algorithms of these codes, as well as their performance and suitability for different types of Flash technology are discussed. Special emphasis is given to the discussion on Low Density Parity Codes (LDPC), which is increasingly being used as an ECC mechanism in today’s NAND Flash devices.