A simulation-based analog IC synthesis tool using SBDE optimization algorithm

Although Analog Integrated Circuits (ICs) only account for a small portion of the entire modern System-on-a-Chip (SoC), their design is one of the most challenging work, demanding extensive knowledge and huge effort. In order to shorten the Time-To-Market (TTM), Electronic Design Automation (EDA) tools are essential for assisting designers by reducing laboring work and helping their decision-making. This thesis presents an analog circuit synthesis tool, which sizes circuits to meet design specifications. The tool adopts the simulation-based approach which encapsulates a SPICE simulator, and uses Selection-Based Differential Evolution (SBDE) as the global optimization algorithm. Synthesis speed is boosted by conducting parallel evaluations, and designer’s preparatory effort is reduced by a user-friendly system architecture without compromising accuracy or flexibility. Three circuit testbenches are synthesized successfully in relatively short time, which demonstrates the effectiveness and efficiency of the tool.