Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Morrison, D.; Delic, D.; Yuce, M. R.; Redouté, Jean-Michel

doi:10.1109/TVLSI.2018.2872021

Article (Scientific journals)

Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Morrison, D.; Delic, D.; Yuce, M. R. et al.

2019 • In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (1), p. 103-115

Peer Reviewed verified by ORBi

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https://hdl.handle.net/2268/239236

DOI
10.1109/TVLSI.2018.2872021

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Keywords :

CMOS integrated circuits; Computer circuits; Decoding; Feedback; Frequency converters; Particle beams; System-on-chip; Binary counters; Large-scale arrays; Linear feedback shift registers; Proof of concept; Single photon detection; System on chip design; Time to digital converters; Shift registers

Abstract :

[en] Linear-feedback shift register (LFSR) counters have been shown to be well suited to applications requiring large arrays of counters and can improve the area and performance compared with conventional binary counters. However, significant logic is required to decode the count order into binary, causing system-on-chip designs to be unfeasible. This paper presents a counter design based on multiple LFSR stages that retains the advantages of a single-stage LFSR but only requires decoding logic that scales logarithmically with the number of stages rather than exponentially with the number of bits as required by other methods. A four-stage four-bit LFSR proof of concept was fabricated in 130-nm CMOS and was characterized in a time-to-digital converter application at 800 MHz. © 1993-2012 IEEE.

Disciplines :

Electrical & electronics engineering

Author, co-author :

Morrison, D.; Department of Electrical and Computer Systems Engineering, Monash University, Clayton, VIC 3800, Australia

Delic, D.; Defence Science and Technology Group, Edinburgh, SA 5111, Australia

Yuce, M. R.; Department of Electrical and Computer Systems Engineering, Monash University, Clayton, VIC 3800, Australia

Redouté, Jean-Michel ; Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés

Language :

English

Title :

Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Publication date :

2019

Journal title :

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSN :

1063-8210

Publisher :

Institute of Electrical and Electronics Engineers Inc.

Volume :

Issue :

Pages :

103-115

Peer reviewed :

Peer Reviewed verified by ORBi

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since 06 September 2019

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