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| Abstract |
近年，LSI の微細化が進み製造ばらつきが深刻になっている．特にチップ内で発生するトランジスタ 特性のランダムなばらつきが問題である．トランジスタ特性のばらつきは回路遅延にばらつきを生じ させる．本研究では，回路遅延の統計的性質に着目し，命令カスケーディングを利用することで回路 遅延ばらつきを縮小することを検討している．しかし，ばらつきに配慮するために，プロセッサの性 能を大きく低下させることは許...容できない．本稿では命令カスケーディングおける命令の重要度に着 目し，性能維持の可能性についての調査を行う.
Due to the aggressively advanced semiconductor technologies, a problem of parameter variations is emerging. Especially, with-in-die variations in transistor performance are very serious. Parameter variations in transistors affect circuit delay. In this paper, we investigate statistical characteristics of circuit delay, and propose to utilize instruction cascading for variation resiliency. An important thing to consider is that performance degradation cannot be accepted even for reduction in variations. In this paper, we exploit instruction criticality to maintain performance of the processor that utilizes instruction cascading.show more
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