Utilize este identificador para referenciar este registo:
http://hdl.handle.net/10362/4057
Título: | New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification |
Autor: | Goes, J. Oliveira, J. P. Paulino, N. Fernandes, J. Paisana, J. |
Data: | Ago-2008 |
Editora: | IEEE |
Resumo: | In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique. |
Descrição: | 15th IEEE International Conference on Electronics, Circuits and Systems, Malta |
URI: | http://hdl.handle.net/10362/4057 |
Aparece nas colecções: | FCT: DEE - Documentos de conferências internacionais |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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Goes_2008.pdf | 271,5 kB | Adobe PDF | Ver/Abrir |
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