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Ganjeheizadeh Rohani, S., Taherinejad, N., & Radakovits, D. (2020). A Semiparallel Full-Adder in IMPLY Logic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(1), 297–301. https://doi.org/10.1109/tvlsi.2019.2936873
E384 - Institut für Computertechnik E384-02 - Forschungsbereich Systems on Chip
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Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ISSN:
1063-8210
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Date (published):
2020
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Number of Pages:
5
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Peer reviewed:
Yes
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Keywords:
Electrical and Electronic Engineering; Software; Hardware and Architecture
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Abstract:
Passive implementation of memristors has led to several innovative works in the field of electronics. Despite being primarily a candidate for memory applications, memristors have proven to be beneficial in several other circuits and applications as well. One of the use cases is the implementation of digital circuits such as adders. Among several logic implementations using memristors, IMPLY logic is one of the promising candidates. In this brief, we present a new architecture for a digital full-adder, which is up to 41% faster than existing IMPLY-based serial designs while requiring up to 78% less area (memristors) compared to the existing parallel design.
en
Research Areas:
Logic and Computation: 70% Computer Science Foundations: 30%
