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Steininger, A., Delvai, M., & Huber, W. (2004). Code Alternation Logic (CAL): A Novel Efficient Design Approach for Delay-Insensitive Asynchronous Circuits. http://hdl.handle.net/20.500.12708/32994
E191-02 - Forschungsbereich Embedded Computing Systems
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Date (published):
2004
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Number of Pages:
0
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Abstract:
As the problems related to clocking synchronous chip designs are becoming more and more severe, asynchronous design methods gain increasing inter- est. Among these the delay insensitive timing model is particularly appealing, since it allows to guaran- tee the correct function completely independent of implementation-dependent delays. In this paper we propose CAL, a new design method for delay ins...
As the problems related to clocking synchronous chip designs are becoming more and more severe, asynchronous design methods gain increasing inter- est. Among these the delay insensitive timing model is particularly appealing, since it allows to guaran- tee the correct function completely independent of implementation-dependent delays. In this paper we propose CAL, a new design method for delay insensitive digital circuits that offers all advantages of the known state based coding techniques. In contrast to existing approaches CAL does not require an explicit unproductive "zero" code between any two data words for synchronization. Instead, CAL uses an alternating code set to represent logic states, which allows one data word to be directly followed by the next one. Obviously this doubles performance while halving energy consumption. While these features make CAL's efficiency comparable to transition based techniques, we show that design, hardware implementation and debugging are much easier for CAL .
