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High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures

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Adriaensen, Stéphane [UCL] Dessard, Vincent [UCL] Delatte, Pierre [UCL] Querol, J.Rovira [UCL] Flandre, Denis [UCL] Richter, S. [UCL]

High-temperature characterization of a 0.8 μm partially-depleted (PD) silicon-on-insulator (SOI) CMOS process is reported. The process is designed for mixed analog/digital/high-voltage applications. The measurements have been realized on n-MOSFETs, on lateral bipolar transistors and on LDMOS transistors and demonstrate the interest of the process under consideration.

Document type Communication à un colloque (Conference Paper) – Présentation orale avec comité de sélection
Publication date 1999
Language Anglais
Conference "Conference HITEN 1999", Berlin (Germany) (du 4/07/1999 au 7/07/1999)
Peer reviewed yes
Host document "Proceedings of HITEN 1999"- 79-82 (ISBN : 0-7803-5795-7)
Publisher IEEE
Affiliation UCL - FSA/ELEC - Département d'électricité
Keywords Bipolar transistors ; Threshold voltage ; CMOS process ; CMOS technology ; Fabrication ; Laboratories ; MOSFET circuits ; Microelectronics ; Space technology ; Temperature
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Bibliographic reference Adriaensen, Stéphane ; Dessard, Vincent ; Delatte, Pierre ; Querol, J.Rovira ; Flandre, Denis ; et. al. High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures.Conference HITEN 1999 (Berlin (Germany), du 4/07/1999 au 7/07/1999). In: Proceedings of HITEN 1999, IEEE1999, p.79-82
Permanent URL http://hdl.handle.net/2078.1/113753