All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Sorée Bart, Magnus Wim, Pourtois Geoffrey, Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode, 10.1007/s10825-008-0217-3
Lee Chi-Woo, Afzalian Aryan, Akhavan Nima Dehdashti, Yan Ran, Ferain Isabelle, Colinge Jean-Pierre, Junctionless multigate field-effect transistor, 10.1063/1.3079411
Cui Yi, Zhong Zhaohui, Wang Deli, Wang Wayne U., Lieber Charles M., High Performance Silicon Nanowire Field Effect Transistors, 10.1021/nl025875l
Shan Yinghui, Ashok S., Fonash Stephen J., Unipolar accumulation-type transistor configuration implemented using Si nanowires, 10.1063/1.2778752
Lu Wei, Xie Ping, Lieber Charles M., Nanowire Transistor Performance Limits and Applications, 10.1109/ted.2008.2005158
Xiang Jie, Lu Wei, Hu Yongjie, Wu Yue, Yan Hao, Lieber Charles M., Ge/Si nanowire heterostructures as high-performance field-effect transistors, 10.1038/nature04796
Doyle B.S., Datta S., Doczy M., Hareland S., Jin B., Kavalieros J., Linton T., Murthy A., Rios R., Chau R., High performance fully-depleted tri-gate CMOS transistors, 10.1109/led.2003.810888
Lee Chi-Woo, Lederer Dimitri, Afzalian Aryan, Yan Ran, Akhavan Nima Dehdashti, Colinge Jean-Pierre, Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs, 10.1016/j.mee.2009.01.061
Jacoboni C., Canali C., Ottaviani G., Alberigi Quaranta A., A review of some charge transport properties of silicon, 10.1016/0038-1101(77)90054-5
Thompson S.E., Armstrong M., Auth C., Alavi M., Buehler M., Chau R., Cea S., Ghani T., Glass G., Hoffman T., Jan C.-H., Kenyon C., Klaus J., Kuhn K., Ma Z., Mcintyre B., Mistry K., Murthy A., Obradovic B., Nagisetty R., Nguyen P., Sivakumar S., Shaheed R., Shifren L., Tufts B., Tyagi S., Bohr M., El-Mansy Y., A 90-nm Logic Technology Featuring Strained-Silicon, 10.1109/ted.2004.836648
Bibliographic reference
Colinge, Jean-Pierre ; Lee, Chi-Woo ; Afzalian, Aryan ; Dehdashti Akhavan, Nima ; Yan, Ran ; et. al. Nanowire transistors without junctions. In: Nature Nanotechnology, Vol. 5, no.3, p. 225-229 (18/01/2010)