Bridging the hardware-software co-design gap in analog compute-in-memory accelerators towards edge CNN classification

With ever-more AI processing requirements at the edge, new computing paradigms become essential to tackle the speed and energy limits of conventional von-Neumann architectures. Amongst them, compute-in-memory (CIM) SRAMs take advantage of genuine data stationarity and massively-parallel analog operations to deliver unprecedented levels of energy/area efficiency, making them excellent candidates for the acceleration of convolutional neural networks (CNNs). However, analog CIM-SRAMs also suffer from several non-idealities that yield approximate calculation results, inducing a key trade-off between computing efficiency and accuracy. Yet, the lack of in-depth understanding of the multi-level CIM design space driving this trade-off nowadays restricts its boundaries. In this thesis, we propose a holistic approach to assess the critical parameters that govern the CIM design space across the whole abstraction stack, from the circuit to the algorithmic level, and leverage it to bridge the gap between promised and real chip performances. To that end, we start by identifying the main circuit-level non-idealities faced by current- and charge-domain CIM-SRAMs, and analyze how these evolve with the numerous hardware parameters. Thence, we develop the ModelCIMs framework to account for these core analog impairments during the CNN training, while also deriving additional bottlenecks for the mapping of CNNs on CIM hardware. Finally, this combined knowledge enables the hardware-software co-design of two mixed-signal CIM-CNN accelerators, respectively embedding 1-to-4b current- and 1-to-8b charge-domain CIM-SRAMs. Notably, both architectures share the ability to reshape data distributions with pre-ADC in-memory gain and offset factors, which is shown to be critical in low-precision designs to avoid significant information loss. Chip measurements of the prototyped accelerators in 22nm FD-SOI demonstrate excellent energy/area efficiency with a mild accuracy degradation on low-complexity datasets, validating our approach.