High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V
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Cita com:
hdl:2117/166596
Tipus de documentArticle
Data publicació2018-01-16
EditorIEEE
Condicions d'accésAccés obert
Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i
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ProjecteCOMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
RYC-2013-14717 (MINECO-RYC-2013-14717)
RYC-2013-14717 (MINECO-RYC-2013-14717)
Abstract
As software continues to control more system-critical functions in cars, its timing is becoming an integral element in functional safety. Timing validation and verification (V&V) assesses softwares end-to-end timing measurements against given budgets. The advent of multicore processors with massive resource sharing reduces the significance of end-to-end execution times for timing V&V and requires reasoning on (worst-case) access delays on contention-prone hardware resources. While Performance Monitoring Units (PMU) support this finer-grained reasoning, their design has never been a prime consideration in high-performance processors - where automotive-chips PMU implementations descend from - since PMU does not directly affect performance or reliability. To meet PMUs instrumental importance for timing V&V, we advocate for PMUs in automotive chips that explicitly track activities related to worst-case (rather than average) softwares behavior, are recognized as an ISO-26262 mandatory high-integrity hardware service, and are accompanied with detailed documentation that enables their effective use to derive reliable timing estimates
CitacióMezzetti, E. [et al.]. High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V. "IEEE Micro", 16 Gener 2018, vol. 38, núm. 1, p. 56-65.
ISSN0272-1732
Versió de l'editorhttps://ieeexplore.ieee.org/document/8259403
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