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ファイル | 記述 | サイズ | フォーマット | |
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transfun.E93.A.2409.pdf | 1.01 MB | Adobe PDF | 見る/開く |
タイトル: | Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence |
著者: | HAGIWARA, Shiho YAMANAGA, Koh TAKAHASHI, Ryo MASU, Kazuya SATO, Takashi https://orcid.org/0000-0002-1577-8259 (unconfirmed) |
著者名の別形: | 佐藤, 高史 |
キーワード: | capacitance power distribution network state-dependency integrated circuit modeling electromagnetic interference |
発行日: | Dec-2010 |
出版者: | The Institute of Electronics, Information and Communication Engineers |
誌名: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
巻: | E93-A |
号: | 12 |
開始ページ: | 2409 |
終了ページ: | 2416 |
抄録: | A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI. |
著作権等: | © 2010 The Institute of Electronics, Information and Communication Engineers |
URI: | http://hdl.handle.net/2433/178697 |
DOI(出版社版): | 10.1587/transfun.E93.A.2409 |
関連リンク: | http://www.ieice.org/jpn/index.html |
出現コレクション: | 学術雑誌掲載論文等 |
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