Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories

Abstract

Three dimensional technology provides high density and bandwidth solutions for high-speed computing. Through-silicon vias (TSVs) are used to interconnect different layers of the stacked dies. Covering for faulty TSVs caused by manufacturing irregularities can be done by including spare TSVs in the chip design and rerouting signals to avoid the problematic vias. Temporary and permanent faulty TSVs can also be produced by other effects such as radiation and mechanical stress. Reed-Solomon (RS) codes are error correcting codes that are able to protect against errors in symbols. A set of bits transmitted through a TSV can be considered as a symbol and protected using RS codes. This article presents a scheme to combine spare TSVs, RS and hardwired seed bits to cope with faulty TSVs.